Technical Field
The solution proposed in this document refers generally to the field of solid state devices, in particular semiconductor devices, and specifically to the field of semiconductor memories. More specifically, the solution proposed in this document refers to the field of the so-called “three-dimensional” (“3D”) semiconductor memories.
State of the Art
In the field of non-volatile semiconductor memories (memory devices capable of retaining the data stored therein even in the absence of an energy supply source), 3D semiconductor memories (“3D memories”) represent an evolution of the traditional “two-dimensional” semiconductor memories (“2D memories”, in which the memory cells are formed as a single layer on a substrate of semiconductor material), which allows to overcome the limits set by the 2D structure to further increment of the integration scale, Therefore, further increases in the storage capacity of data per unit area can be achieved.
Examples of non-volatile 3D semiconductor memory devices with NAND architecture (in which there are groups of memory cells connected in series to form strings of memory cells) are described both in non-patent literature and in various patents/patent applications, among others U.S. Pat. No. 9,218,874, U.S. 2015/017771 A1 and U.S. 2014/0293695.
In particular, U.S. Pat. No. 9,218,874 describes an architecture in which there are strings of memory cells in the form of pillars which extend, in one direction, from a first end to a second end opposite the first end along said direction. U.S. 2015/017771 and U.S. 2014/0293695 describes instead a different architecture in which the strings of memory cells have generally a “U” shape, each of the strings comprising two pillars, extending parallel to each other along one direction, each pillar having a first end and a second end, and the second ends being connected to each other.